1. Field of the Invention
A converter circuit is disclosed herein with particular attention given to the method of regulating the output signal of the converter. Specifically described is the operation of the switching devices of the converter and how this operation is controlled to secure regulation of the converter output signal.
2. Prior Art
A typical converter circuit of the prior art having a double-ended, push-pull type configuration is shown in FIG. 1 of the drawings. This converter circuit includes two switching devices which are alternately pulse width modulated to secure regulation of the converter output signal. The two switching devices comprise two alternately switched switching transistors 110 and 120 whose main conductive paths couple the primary winding 103 of a power transformer 101 to a ground terminal of a voltage source 104. The other terminal of the voltage source 104 is coupled to a center tap 100 of the primary winding 103 via a lowpass filter including the inductor 105 and the capacitor 106. The output winding 102 of the power transformer 101 is connected to a rectifier comprising the rectifying diodes 113 and 114 which in turn are connected to an output lowpass filter including the inductor 107 and the capacitor 108. A resistive load 109 to be energized is connected across the capacitor 108. Two voltage sensing leads 125 and 126 connect opposite terminals of the load 109 to a regulation control circuit 116. The regulation control circuit 116 includes an internal reference signal with which the load voltage is compared. The regulation control circuit 116 generates bias signals which are coupled to the base electrodes 111 and 121 to control the conductivity of the switching transistors 110 and 120 to maintain the desired output voltage at the load 109.
The operation of this typical converter circuit may be readily explained with reference to FIG. 2 which discloses waveforms illustrating the signals occurring within the converter circuit. The regulation control circuit 116 in response to the output voltage signal sensed by leads 125 and 126 applies bias signals to the base electrode 111 and the base electrode 121 to control the alternate duration of conduction of the transistors 110 and 120, respectively, in order to regulate the output signal of the converter. The alternate intervals of conduction of the transistors 110 and 120 are shown by the waveforms Q.sub.1 and Q.sub.2, respectively. The solid lines 201 and 202 of waveforms Q.sub.1 and Q.sub.2 represent the alternate conduction intervals of transistors 110 and 120, respectively. The conduction duration intervals a.sub.1, a.sub.3, and a.sub.5 shown in FIG. 2 represent the successive conduction intervals of the transistor 110. The conduction duration intervals b.sub.2, b.sub.4, and b.sub.6 represent the successive conduction intervals of the transistor 120. As is apparent from the waveforms Q.sub.1 and Q.sub. 2, the conduction intervals of transistors 110 and 120 are mutually exclusive. At no time do both of the transistors 110 and 120 conduct simultaneously. An interval of nonconduction x occurs between the alternate conduction intervals a and b.
The voltage waveform VQ.sub.1 represents the voltage drop across transistor 110, and the voltage waveform VQ.sub.2 represents the voltage drop across transistor 120. During the conducting interval a.sub.1, it is apparent from the waveform VQ.sub.1 that the voltage drop across transistor 110 is either zero or a very small value since transistor 110 is in its saturated conduction state. As soon as the conducting interval a.sub.1 is terminated, a voltage spike 203 appears across transistor 110. This spike decays and the voltage subsequently rises to the steady state voltage value shown by the voltage level 204. This steady state voltage value is approximately twice the voltage of source 104. Similarly, the voltage drop across transistor 120 at the end of conduction interval b.sub.2 rises to a peak value shown by the spike waveform 205 and subsequently decays and then rises to a steady state voltage level 206 which is approximately twice the voltage of source 104. The voltage spikes 203 and 205 are due to the reverse EMF of the transformer 101 when current conduction is initially cut off in the primary winding 103.
The output voltage appearing across the secondary winding 102 is shown by the voltage waveform V.sub.s. The voltage spikes 207 and 208 occur coincident with the voltage spikes 203 and 205 of waveforms VQ.sub.1 and VQ.sub.2, respectively. The voltage spikes 207 and 208 decay and the subsequent square wave voltage waveform 219 is generated coincident with the conducting intervals of the two switching transistors 110 and 120. This square wave voltage appears across the secondary winding 102 of the converter. The abrupt switching of transistors 110 and 120, in conjunction with the nonconducting intervals x of the two switching transistors 110 and 120, generates the current waveform spikes in the current waveform I.sub.1. This current waveform spike occurs when the transistors 110 and 120 are switched into their conducting state. For example, the current spike 209 of the current waveform representing the current I.sub.1 flowing through the center tap 100 of the primary winding 103 occurs when the transistor 110 is biased into its conducting state. This spike rapidly decays and the current subsequently gradually increases as shown by ramp function current waveform 210.
In general, the regulation control 116 alternately drives the switching transistors 110 and 120 with square wave pulse bias signals. The two transistors 110 and 120 are alternately switched into conduction. The current flowing through each transistor is directed through opposite halves of the center tapped primary winding 103 of the transformer 101. This results in the approximate square wave voltage V.sub.s occurring across the secondary winding 102.
The typical push-pull type converter circuit, as described above, generally requires many circuit components in addition to those shown to compensate for the inherently disadvantageous characteristics of the converter circuit. For example, the input impedance of a conventional push-pull converter tends to be capacitive, causing large inrush currents when the ciruit is initially energized.
As shown by the above-described waveforms, peak transient voltages and currents occur due to the conduction discontinuity when both switching transistors are biased nonconducting. This requires large capacity switching transistors and converter power transformers to deal with these peak transient currents and voltages. In addition, symmetry correction is frequently necessary to prevent the transformer from drifting into saturation due to unequal parameter characteristics of the two switching transistors. A converter circuit such as disclosed in FIG. 1 normally requires both an input filter and an output filter. Should the converter circuit have multiple outputs, a filter inductor is required for each of the individual outputs.